The invention relates to the field of information technology and, more particularly, to a method for controlling memory access on a machine with non-uniform memory access distributed over several modules and a machine implementing the method.
In the field of information technology, it is possible to increase the power of a machine by increasing the number of processors of which it is composed. One type of machine known by the name SMP allows the various processors of the same machine to access its memory symmetrically by means of a system bus. These are machines with uniform memory access in so far as the time to access the memory is substantially the same for all the data accessed. However, the performance curve of such machines does not increase linearly as a function of the number of processors. A high number of processors means that the machine manages more problems of accessibility to its resources than it has resources to execute applications. This has the consequence of considerably distorting the performance curve when the number of processors exceeds an optimal number, often estimated to be of the order of four. The state of the art offers different solutions to this problem.
A known solution consists in grouping several machines in clusters so as to make them communicate together by means of a network. Each machine has an optimal number, for example four processors, and its own operating system. It establishes communication with another machine each time it performs processing of data kept updated by that other machine. The time needed for these communications and the need to work on coherent data pose problems of latency for bulky applications such as distributed applications, which require numerous communications. Latency is the period separating the moment of sending a request to access the memory and the moment when the response to this request is received.
Another known solution is that of NUMA-type machines. These are machines with non-uniform memory access, in so far as the memory access time varies according to the location of the data accessed. A NUMA-type machine is constituted by several modules, each module comprising an optimal number of processors and a physical portion of the total memory of the machine. Such a machine has non-uniform memory access since it is generally easier for a module to access a physical portion of the memory that it does not share with another module than with a portion that it shares. Although each module has a private system bus connecting its processors and its physical memory, an operating system common to all the modules means that all the private system buses can be considered one single system bus of the machine. Logical addressing assigns a place of residence to a given physical memory location in a module. For a processor being considered, a distinction is drawn between accesses to a local portion of memory, physically located on the same module as the processor, and accesses to a remote portion of memory, physically located on one or more modules other than the one where the processor is located.
A particular type of NUMA machine is the CCNUMA type, i.e. the type of machine with what is known as cache coherency. A shared cache mechanism means that, at any given moment, a valid, i.e. updated, copy of this block is not necessarily located in its physical memory location of residence. One or more updated copies of the block can in this way migrate from one module to the other in line with application demands and system calls. The physical memory, located in a module under consideration, is that which the module under consideration accesses most quickly, since it does this directly by means of its local system bus. The physical memory, remote in another module, is the one which the module under consideration accesses least quickly, since it requires one or more transactions between modules. The physical memory, local to the module under consideration, comprises a first portion specially assigned to the data blocks resident in that module, and a second portion specially assigned to copies of blocks resident in other modules. The second portion of physical memory constitutes a remote memory cache in the other modules.
A block resident in the first portion of physical memory is not immediately available if its content does not constitute an updated copy, this is the case, for example, if one or more other modules share this block and if one of these other modules holds an updated copy thereof, in terms of memory coherency. To manage the sharing of blocks resident in its first portion of physical memory with other modules, the module under consideration has a remote cache controller RCC.
The usefulness of machines with non-uniform memory access and cache coherency is that each module works on data blocks resident in a first portion of its local memory or on copies in a second portion of local memory, of blocks resident in a first portion of memory of another module. A module under consideration then needs to communicate with other modules only in order to work on updated copies so as to ensure data coherency. In execution, it is therefore a priori immaterial whether a block of data is resident in one module or another since, if necessary, each module relocates in its local memory copies of blocks that it needs. However, for executing the operating system common to all the modules or certain applications of distributed type, it is possible that certain data may be useful to all the modules. By way of non-exhaustive example, these data concern process allocation tables, open file tables or tables of the setting of locks on shared resources. The coherency of these data is likely to need numerous exchanges between modules and therefore to interfere with the increase of performance expected of such machines.
On the other hand, it is of interest to use a virtual addressing mode in order to get an information processing machine to execute processes. As known in the state of the art, a virtual addressing space is allocated to each process executed by the machine. The virtual addressing machine makes it possible to free itself of the constraints of memory size that can occur in a physical addressing space. The processes and the tasks (otherwise known as threads) within a process access their virtual addressing space by means of effective addresses that generate logical page numbers, to each of which the machine causes a physical page number (otherwise known as a frame) to correspond, this being accessible in physical memory, as actual access needs arise. The virtual memory mechanism is independent of the cache coherency mechanism. However, if a process task is executed on a processor located on a module that is different from the module in the memory of which a physical page, accessed by that task, is resident, the implementation of the cache coherency protocol between modules is likely to slow down memory accesses and impair the performance of the system.
The complexity of the correlation mechanisms and the physical memory requirements of the numerous processes executed by the machine mean that it is difficult to apprehend a priori the distribution of the physical pages over the modules so as to correspond to logical pages.
The invention proposes a method for controlling memory access on a machine with non-uniform memory access distributed over several modules, each module comprising one or more processors CPU for executing tasks on a virtual or physical addressing space by means of effective addresses EA generating logical page numbers LPN to which it is possible to make physical page numbers PPN correspond in said memory by means of a correlation table LPT, the generation of a logical page number LPN causing a first-level page-fault type exception when said logical page number LPN is absent from the correlation table, characterised in that it comprises a step for activating, following each first-level page-fault type exception, a trace function, which records the value of the effective address EA that has generated the logical page number LPN that has caused said exception, the date when said exception is caused, an identifier of the task using said effective address EA, an identifier of the processor executing said task and the physical page number PPN corresponding to the logical page number that has caused said exception.
The activation of the trace function at each first-level page-fault type exception makes it possible to detect each new first access by a processor to a page of physical memory, whether or not this page is pegged. The identifier of the processor and the physical page number make it possible to know which module is the location of the physical page and the processor. There is good affinity between processor and physical memory if they are located in the same module. The date makes it possible to define the moment when this new first access occurred, it allows the trace results to be correlated between each other or with other results obtained elsewhere. The task identifier makes it possible to know the task to which the memory access is linked and thus to correlate various memory accesses linked to the same task, which can for example be executed on different processes over the course of time. The value of the effective address makes it possible to specify the type of addressing used by the task, the physical page number associated with any one effective address can evolve over the course of time if the physical page is not pegged. In order to communicate, various tasks can use the same effective address.
By starting up the method at the same time as executing processes on the machine, one is sure of detecting all the configurations of access to the physical memory. For starting up the method independently of executing processes on the machine, the invention proposes invalidating all the inputs in the correlation table LPT when starting up the method.
The invention also proposes a machine for implementing the method of controlling memory access, comprising first means for activating a function that introduces a logical page number LPN with a correlation to the physical page number PPN in a correlation table following an exception caused by an absence of valid input containing said logical page number LPN in said correlation table, characterised in that it comprises:
second means to replace the first means by third means, which activate a trace function.